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B<Verilog::CodeGen>
Verilog code generator

B<Verilog::CodeGen> - Verilog code generator


SYNOPSIS


  use Verilog::CodeGen;

  mkdir 'DeviceLibs/Objects/YourDesign', 0755;

  chdir 'DeviceLibs/Objects/YourDesign';

  

  # if the directory YourDesign exists, the second argument can be omitted 

  # create YourModule.pl in YourDesign 

  &create_template_file('YourModule','YourDesign');

  # create a device library for testing in DeviceLibs/Objects/DeviceLibs

  &make_module('YourModule','YourDesign');

  # create the final device library in DeviceLibs (once YourModule code is clean)

  &make_module('','YourDesign');


USAGE

The most efficient way to use the code generator is using the GUI (scripts/gui.pl in the distribution). Read the documentation in the Verilog::CodeGen::Gui.pm manpage). Alternatively, you can use the scripts that the GUI uses to do the work (in the scripts/GUI folder). If you want to make your own, follow the SYNOPSIS.

Then edit the file YourModule.pl in the folder DeviceLibs/Objects/YourDesign.

For example:


        sub gen_YourModule {    

        my $objref=shift;

        my $par=$objref->{parname}||1;

        # Create Objects

        my $submodule=new('SubModule',parname1=>$par);

        # Instantiate

        

        my $pins="(A,Z)";

        my $modname=$objref->{modulename};

        my $code = "

        module $modname $pins;

        input A;

        output Z;

        ";

        $code.=$submodule->inst('suffix',P1=>'A');

        $code .="

        endmodule // $modname

        ";

        $objref->{pins}=$pins;

        return $code;

        } # END of gen_YourModule

Then run perl YourModule.pl to check if the code produces valid a Verilog module.

If this is the case, add YourModule to the device library with &make_module()

Next, create a testbench test_YourModule.pl in a directory on the same level as DeviceLibs (TestObj if you use the GUI):




        use lib '..';

        use DeviceLibs::YourDesign;

        my $device=new("S_buffer_demux",depth=>7,);

        open (VER,">test_S_buffer_demux.v");

        output(*VER);

        modules();

        print VER "

        module test_S_buffer_demux;

           wire A;

           wire [7:0] S;

           wire [6:0] Z;

           wire D;

        

           reg a;

           reg [7:0] s;

        

        assign    A=   a;

        assign     S=    s;

        

        reg _ck;

        ";

        $device->instance();

        my $x=$device->{""};

        print VER "

        // clock generator

        always begin: clock_wave

           #10 _ck = 0;

           #10 _ck = 1;

        end

        

        always @(posedge _ck)

        begin

        \$display(\" \%0d  \%b \%b \",\$time,$x.   Z,$x.   D);

        end

        initial 

        begin

        \$display(\"Time     Z    D\");

        a<=1;

        #25;

        a<=0;

        #25;

        \$finish;

        end

        endmodule

        ";

        close VER;

        run("test_S_buffer_demux.v");

        #plot("test_S_buffer_demux.v");

Execute the testbench script with perl test_YourModule.pl.


DESCRIPTION

Provides an object-oriented environment to generate Verilog code for modules and testbenches. The Verilog::CodeGen module provides two functions, one to create a code template and another to create a Perl module which contains the device library. This module , DeviceLibs::YourDesign, provides the class methods and contains the objects for every Verilog module; the objects are created based on a fixed template. The purpose of this module is to allow the generation of customized Verilog modules. A Verilog module can have a large number of parameters like input and output bus width, buffer depth, signal delay etc. The code generator allows to create an object that will generate the Verilog module code for arbitraty values of the parameters.


UTILITY SCRIPTS

With the Perl module distribution come a number of utility scripts. The most important one is gui.pl, a GUI frontend for Verilog development using the code generator.


MAIN METHODS

new($object_name[,%attributes]);

Create a new Verilog module object. The object attributes are optional, the object should provide reasonable defaults.

output([*filehandle_ref||$filename])

output() takes a reference to a filehandle or a filename as argument. These are stored in the global %printcfg. Without arguments, this defaults to STDOUT. If output() is called with as argument a string containing \n and/or \s, this string is printed on the current filehandle.

modules

The code generator stores all submodules of a given module in the global %modules. Calling modules() prints the code for these modules on the current filehandle.

instance([$instance_suffix,%connectivity])

The instance() method will print the code for the instantiation of the object on the current filehandle. An optional instance suffix can be specified (to distinguish between different instances of the same module), as well as the pin connectivity. If the connectivity for a pin is not specified, it defaults to the pin name.

inst([$instance_suffix,%connectivity])

The inst() method will return the code for the instantiation of the object as a string. An optional instance suffix can be specified (to distinguish between different instances of the same module), as well as the pin connectivity. If the connectivity for a pin is not specified, it defaults to the pin name.

run([$filename])

Run the netlist through the Icarus Verilog (http://www.icarus.com) open source verilog simulator. The filename is optional if it was specified with the output() method.

plot([$filename])

Plot the result of the simulation with gtkwave. For this purpose, the \$dumpvar and \$dumpfile compiler directives must be present in the testbench code. The filename is optional if it was specified with the output() method.

module('modulename')

This method can be used to print the code for a specified module on the current filehandle.

search(/pattern/)

Search the verilog code for a given pattern.

find_inst(/pattern/)

Find all instances matching /pattern/ in the netlist.


MAIN ATTRIBUTES

{$instance_suffix}

Returns the full instance name of the object. $x=$object->{$instance_suffix};


TODO

  • Convert the utility scripts to functions to be called from Verilog::CodeGen.

  • Put the GUI scripts in a module Gui.pm.

  • Separate the code for testing purposes from the module object code.


SEE ALSO

Icarus Verilog http://icarus.com/eda/verilog/index.html


AUTHOR

W. Vanderbauwhede wim@motherearth.org.

http://www.comms.eee.strath.ac.uk/~wim


COPYRIGHT

Copyright (c) 2002 Wim Vanderbauwhede. All rights reserved. This program is free software; you can redistribute it and/or modify it under the same terms as Perl itself.

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