Help-Site Computer Manuals
Software
Hardware
Programming
Networking
  Algorithms & Data Structures   Programming Languages   Revision Control
  Protocols
  Cameras   Computers   Displays   Keyboards & Mice   Motherboards   Networking   Printers & Scanners   Storage
  Windows   Linux & Unix   Mac

Verilog::Netlist::Module
Module within a Verilog Netlist

Verilog::Netlist::Module - Module within a Verilog Netlist



NAME

Verilog::Netlist::Module - Module within a Verilog Netlist


SYNOPSIS


  use Verilog::Netlist;

  ...

  my $module = $netlist->find_module('modname');

  my $cell = $self->find_cell('name')

  my $port =  $self->find_port('name')

  my $net =  $self->find_net('name')


DESCRIPTION

A Verilog::Netlist::Module object is created by Verilog::Netlist for every module in the design.


ACCESSORS

See also Verilog::Netlist::Subclass for additional accessors and methods.

$self->cells
Returns list of references to Verilog::Netlist::Cell in the module.

$self->cells_sorted
Returns list of name sorted references to Verilog::Netlist::Cell in the module.

$self->comment
Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.

$self->find_port_by_index
Returns the port name associated with the given index.

$self->is_top
Returns true if the module has no cells referencing it (is at the top of the hierarchy.)

$self->name
The name of the module.

$self->netlist
Reference to the Verilog::Netlist the module is under.

$self->nets
Returns list of references to Verilog::Netlist::Net in the module.

$self->nets_sorted
Returns list of name sorted references to Verilog::Netlist::Net in the module.

$self->nets_and_ports_sorted
Returns list of name sorted references to Verilog::Netlist::Net and Verilog::Netlist::Port in the module.

$self->ports
Returns list of references to Verilog::Netlist::Port in the module.

$self->ports_ordered
Returns list of references to Verilog::Netlist::Port in the order the ports were declared in the module's port list.

$self->ports_sorted
Returns list of name sorted references to Verilog::Netlist::Port in the module.


MEMBER FUNCTIONS

See also Verilog::Netlist::Subclass for additional accessors and methods.

$self->autos
Updates the AUTOs for the module.

$self->find_cell(name)
Returns Verilog::Netlist::Cell matching given name.

$self->find_port(name)
Returns Verilog::Netlist::Port matching given name.

$self->find_net(name)
Returns Verilog::Netlist::Net matching given name.

$self->lint
Checks the module for errors.

$self->link
Creates interconnections between this module and other modules.

$self->modulename_from_filename
Uses a rough algorithm (drop the extension) to convert a filename to the module that is expected to be inside it.

$self->new_cell
Creates a new Verilog::Netlist::Cell.

$self->new_port
Creates a new Verilog::Netlist::Port.

$self->new_net
Creates a new Verilog::Netlist::Net.

$self->dump
Prints debugging information for this module.

$self->verilog_text
Returns verilog code which represents this module. Returned as an array that must be joined together to form the final text string.


DISTRIBUTION

Verilog-Perl is part of the http://www.veripool.com/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.com/verilog-perl.html.

Copyright 2000-2007 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License or the Perl Artistic License.


AUTHORS

Wilson Snyder <wsnyder@wsnyder.org>


SEE ALSO

Verilog-Perl, the Verilog::Netlist::Subclass manpage the Verilog::Netlist manpage

Programminig
Wy
Wy
yW
Wy
Programming
Wy
Wy
Wy
Wy