Help-Site Computer Manuals
Software
Hardware
Programming
Networking
  Algorithms & Data Structures   Programming Languages   Revision Control
  Protocols
  Cameras   Computers   Displays   Keyboards & Mice   Motherboards   Networking   Printers & Scanners   Storage
  Windows   Linux & Unix   Mac

Verilog::Netlist::Pin
Pin on a Verilog Cell

Verilog::Netlist::Pin - Pin on a Verilog Cell



NAME

Verilog::Netlist::Pin - Pin on a Verilog Cell


SYNOPSIS


  use Verilog::Netlist;

  ...

  my $pin = $cell->find_pin ('pinname');

  print $pin->name;


DESCRIPTION

A Verilog::Netlist::Pin object is created by Verilog::Netlist::Cell for for each pin connection on a cell. A Pin connects a net in the current design to a port on the instantiated cell's module.


ACCESSORS

See also Verilog::Netlist::Subclass for additional accessors and methods.

$self->cell
Reference to the Verilog::Netlist::Cell the pin is under.

$self->comment
Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.

$self->delete
Delete the pin from the cell it's under.

$self->module
Reference to the Verilog::Netlist::Module the pin is in.

$self->name
The name of the pin. May have extra characters to make vectors connect, generally portname is a more readable version. There may be multiple pins with the same portname, only one pin has a given name.

$self->net
Reference to the Verilog::Netlist::Net the pin connects to. Only valid after a link.

$self->netlist
Reference to the Verilog::Netlist the pin is in.

$self->netname
The net name the pin connects to.

$self->portname
The name of the port connected to.

$self->port
Reference to the Verilog::Netlist::Port the pin connects to. Only valid after a link.


MEMBER FUNCTIONS

See also Verilog::Netlist::Subclass for additional accessors and methods.

$self->lint
Checks the pin for errors. Normally called by Verilog::Netlist::lint.

$self->dump
Prints debugging information for this pin.


DISTRIBUTION

Verilog-Perl is part of the http://www.veripool.com/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.com/verilog-perl.html.

Copyright 2000-2007 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License or the Perl Artistic License.


AUTHORS

Wilson Snyder <wsnyder@wsnyder.org>


SEE ALSO

Verilog-Perl, the Verilog::Netlist::Subclass manpage the Verilog::Netlist manpage

Programminig
Wy
Wy
yW
Wy
Programming
Wy
Wy
Wy
Wy