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Verilog-Perl
Overview of Verilog language packages for Perl

Verilog-Perl - Overview of Verilog language packages for Perl



NAME

Verilog-Perl - Overview of Verilog language packages for Perl


DESCRIPTION

The Verilog-Perl distribution provides Perl parsing and utilities for the Verilog Language. This file provides an overview of the distribution, for specific details on each component, see that component's manpage.

You may also want to try the AUTO features present in http://www.veripool.com/verilog-mode.html Verilog-Mode.


INSTALLATION

Skip this section if Verilog-Perl has already been installed.

Supported Systems

Verilog-Perl should run on any system with Perl, G++, Flex, and Bison. It is known to work on at least:

CPAN Installation

Easiest installation is using the ``CPAN'' command line that comes with Perl. After configuring CPAN the first time, simply


   $ cpan

   cpan> install Verilog-Perl

Read the rest of this file for details on the programs provided.

Manual Installation

Download the latest version from http://www.perl.org/CPAN/, or from http://www.veripool.com/verilog-perl.html.

cd to the directory containing this README notice.

Type perl Makefile.PL to configure Verilog for your system.

Type make to compile Verilog. Some Solaris users have had trouble with ``open'' being redefined. If this happens, try editing the Makefile to change _FILE_OFFSET_BITS to 32 instead of 64.

Type make test to check the package. If you don't have Synopsys' VCS, the test will print a warning, which you can ignore.

Type make install to install the programs and any data files and documentation.

Read the rest of this file for details on the programs provided.


SCRIPTS

The following scripts are installed by Verilog-Perl:

vhier
Vhier reads the Verilog files passed on the command line and outputs a tree of all of the filenames, modules, and cells referenced by that file.

vpm
Vpm will read the specified Verilog files and preprocess special PLI assertions.

vppp
Vppp reads the Verilog files passed on the command line and outputs preprocessed output.

vrename
Vrename will allow a signal to be changed across all levels of the design hierarchy, or to create a cross reference of signal names.


PACKAGES

Verilog::Getopt
Verilog::Getopt provides standardized handling of options similar to Verilog/VCS and cc/GCC.

Verilog::Language
Verilog::Language provides general utilities for using the Verilog Language, such as parsing numbers or determing what keywords exist.

Verilog::Netlist
Verilog::Netlist reads and holds interconnect information about a whole design database.

Verilog::Netlist::Cell
A Verilog::Netlist::Cell object is created by Verilog::Netlist for every instantiation in the current module.

Verilog::Netlist::File
Verilog::Netlist::File allows Verilog::Netlist objects to be read and written in Verilog format.

Verilog::Netlist::Module
A Verilog::Netlist::Module object is created by Verilog::Netlist for every module in the design.

Verilog::Netlist::Net
A Verilog::Netlist::Net object is created by Verilog::Netlist::Module for every signal and input/output declaration in the current module.

Verilog::Netlist::Pin
A Verilog::Netlist::Pin object is created by Verilog::Netlist::Cell for for each pin connection on a cell.

Verilog::Netlist::Port
A Verilog::Netlist::Port object is created by Verilog::Netlist::Module for every port connection in the module.

Verilog::Netlist::Subclas
The Verilog::Netlist::Subclass is used as a base class for all Verilog::Netlist::* structures.

Verilog::Parser
Verilog::Parser will tokenize a Verilog file and invoke various callback methods.

Verilog::Preproc
Verilog::Preproc reads Verilog files, and preprocesses them according to the Verilog specification. Programs can be easily converted from reading a IO::File into reading preprocessed output from Verilog::Preproc.

Verilog::SigParse
Verilog::SigParser builds upon the Verilog::Parser package to provide callbacks for when a signal is declared, a module instantiated, or a module defined.


WHICH PARSER PACKAGE?

If you are starting a new application which needs to parse the Verilog language you have several tools available to you. Which you pick depends on how low level and complete the information you need is.

Verilog::Preproc
Verilog::Preproc is useful when you need only text out, or a list of defines, etc. It can preprocess a file, or be used to provide the Verilog macro language on top of synthesis scripts. It understands the full SystemVerilog 2005 preprocessor syntax.

Verilog::Parser
Verilog::Parser is useful when you need to tokenize or write source filters (where you need everything including whitespace). It can take raw files, or preprocessed input. It understands all SystemVerilog 2005 keywords.

Verilog::SigParser
Verilog::SigParser is useful when you need a list of modules, signals, ports, functions, etc. It requires a preprocessed file, and can parse most Verilog 2005 files, but only provides callbacks on certain interesting things. It does not have SystemVerilog support yet; try contacting the author with your requirements.

Verilog::Netlist
Verilog::Netlist is useful for when you need the hierarchy, and a list of signals per module, pins per cell, etc. It builds upon the output of Verilog::SigParser, so requires preprocessed files. It does not have SystemVerilog support yet.

This is probably the most popular choice.

VPI
Using the VPI is the best way to access the behavior of the design. It is not part of this package as it requires a compliant simulator and C++ code to call the VPI, and understands as much of the language as the simulator supports. This allows writing lint checks and full knowledge of all parts of the code, but generally requires the most work (short of writing a parser from scratch.)


DISTRIBUTION

Verilog-Perl is part of the http://www.veripool.com/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.com/verilog-perl.html.

Copyright 2000-2007 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License or the Perl Artistic License.

This code is provided with no warranty of any kind, and is used entirely at your own risk.


AUTHORS

Wilson Snyder <wsnyder@wsnyder.org>


SEE ALSO

vhier, vpm, vppp, vrename

the Verilog::EditFiles manpage, the Verilog::Getopt manpage, the Verilog::Language manpage the Verilog::Netlist manpage, the Verilog::Parser manpage, the Verilog::Preproc manpage, the Verilog::SigParser manpage

the Verilog::Netlist::Cell manpage, the Verilog::Netlist::File manpage, the Verilog::Netlist::Module manpage, the Verilog::Netlist::Net manpage, the Verilog::Netlist::Pin manpage, the Verilog::Netlist::Port manpage, the Verilog::Netlist::Subclass manpage,

And the http://www.veripool.com/verilog-mode.htmlVerilog-Mode package for Emacs.

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